![]() Support for new layers can be added as they become available.Įarly customers are already in design with the Vision C5 DSP. The Vision C5 DSP supports variable kernel sizes, depths, and input dimensions, and it accommodates several different coefficient compression/decompression techniques. As such, it leverages a comprehensive set of hand-optimized neural network library functions. Because of the very computing-intensive SAR. ![]() The toolset will map any neural network trained with tools such as Caffe and TensorFlow into executable and highly optimized code for the Vision C5 DSP. Unlike optical observation methods, SAR pulses require intensive signal processing before rendering a visible image. If you?re concerned about designing with or programming the core, rest assured that it comes with the Cadence neural network mapper toolset, the same proven software toolset as the Vision P5 and P6 DSPs. Hence, the performance can scale based on application needs. It?s also architected for multi-processor designs. This frees up the host processor to handle other tasks. Note that the C5 DSP is not an accelerator, per se, but rather a complete, standalone DSP IP core that runs all neural network layers (convolution, fully connected, pooling and normalization). From a silicon perspective, the IP core consumes about 1 mm 2 of die area. ![]() Specifically, the Vision C5 DSP is aimed at automotive, surveillance, drone, and mobile/wearable applications, as it offers 1 TMAC/s computational capacity to run all neural network computational tasks. Tensilica claims that the IP core is the industry?s first standalone, self-contained neural network DSP IP core optimized for vision, radar/lidar, and fused-sensor applications with high-availability neural network computational needs. Times are obviously changing, as evidenced by Cadence?s Vision C5 DSP (which actually comes for the company?s Tensilica division). It wasn?t long ago that a system employing neural networks requires a host of big CPUs, and lots of associated board area. ![]()
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